This invention claims priority from Japanese Patent Application No. 2006-230730 filed on Aug. 28, 2006, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device which achieves higher reliability by reducing resistance of the device.
2. Description of the Related Art
In many discrete semiconductor devices (semiconductor chips), electrodes connected to an input terminal and an output terminal, respectively, are provided above the respective surfaces (front and rear surfaces) of the chip, respectively. Meanwhile, there has also been known a type of a semiconductor device having both electrodes provided above one surface of a chip to enable flip-chip mounting or the like.
With reference to FIG. 12, a conventional flip-chip mountable semiconductor device will be described by taking a MOSFET as an example.
On an n+ type semiconductor substrate 133, an n− type epitaxial layer is provided to obtain a drain region 134. In the drain region 134, a p type channel layer 135 is provided. Thereafter, a trench 136 that reaches the drain region 134 is formed from a surface of the channel layer 135. Subsequently, an inner wall of the trench 136 is covered with a gate oxide film 137, and a gate electrode 138 is provided in the trench 136. Thus, each cell 132 is formed. In the surface of the channel layer 135 adjacent to the trench 136, an n+ type source region 139 and a p+ type body region 140 are formed. The trench 136 is covered with an interlayer insulating film 141.
A source electrode 142 is provided by sputtering Al or the like so as to be connected to the source region 139 in each cell 132. A gate pad electrode 148 is an electrode formed in the same step as that of the source electrode 142 and allows the gate electrode to come into contact therewith by extending the gate electrode. A drain pad electrode 114 is an electrode formed in the same step as that of the source electrode 142 and is provided on an annular 115 in a periphery of the semiconductor chip.
A source bump electrode 111 is a solder bump which comes into contact with the source electrode 142. A contact hole is provided in a nitride film 156 on the source electrode 142, and a base electrode 110 to be a base for solder. Thereafter, the solder bump is formed thereon. A gate bump electrode 112 and a drain bump electrode 113 are also solder bumps provided in the same manner as the source bump electrode 111.
As a metal plate 116, a metal piece, such as Cu, Fe and Al, smaller than a chip size is attached to a rear surface of the semiconductor chip in accordance with coordinates for chip arrangement on a wafer. This metal plate 116 can reduce a drain resistance.
As described above, electrodes connected to all terminals, such as electrodes (source and drain electrodes) connected to an input terminal and an output terminal and, in this case, an electrode (gate electrode) connected to a control terminal, are provided above a first surface of a semiconductor substrate (semiconductor chip). Thus, the chip can be flip-chip mounted. This technology is described, for instance, in Japanese Patent Application Publication No. 2002-368218.
FIGS. 13A and 13B are views schematically showing arrangement of an electrode (for example, a source electrode S) connected to an input terminal IN and an electrode (for example, a drain electrode D) connected to an output terminal OUT and a resistance component of a current path formed in a substrate in a discrete MOSFET.
FIG. 13A shows the case where the source electrode S and the drain electrode D are provided on a first surface Sf1 and a second surface Sf2, respectively. FIG. 13B shows the case where both of the source electrode S and the drain electrode D are provided on the first surface Sf1.
As a substrate, a low-concentration semiconductor layer LS is laminated on a high-concentration semiconductor substrate HS. Moreover, in a surface of the low-concentration semiconductor layer LS, an element region e of the MOSFET is provided.
In the case of FIG. 13A, a current path is formed as indicated by the arrow, which reaches the drain electrode D on the second surface Sf2 from the source electrode S on the first surface Sf1 through the low-concentration semiconductor layer LS and the high-concentration semiconductor substrate HS. Therefore, in this case, a resistance component from the source electrode S toward the drain electrode D in the MOSFET is mainly set to be a resistance Ra in a depth (vertical) direction of the substrate.
In such a conventional power MOSFET, the drain electrode D is taken out from a rear surface (the second surface Sf2) of a semiconductor chip. Thus, the current path is formed in the depth (vertical) direction of the substrate. Therefore, in this case, the drain electrode D on the rear surface is formed to have a thickness as small as possible in order to further reduce a drain resistance.
For example, Ti that improves adhesion and Ni that prevents diffusion of solder toward Si are formed to have thicknesses of 500 Å and 5000 Å, respectively. Thereafter, Au is formed to have a thickness of 500 Å.
In the case where the semiconductor chip described above is to be, for example, flip-chip mounted, it is necessary to provide the drain electrode D on the same plane as the source electrode S. In this case, a current path is formed from the source through the substrate to the drain. However, if a metal layer (the drain electrode D) on the rear surface still has a small thickness as shown in FIG. 13A, a resistance value is increased.
Meanwhile, FIG. 13B shows a structure suitable for flip-chip mounting and shows, for example, the case of the conventional structure shown in FIG. 12. In such a structure in which the source electrode S and the drain electrode D are provided on the first surface Sf1 of the chip, a current path is formed as indicated by the arrows, which reaches the low-concentration semiconductor layer LS and the high-concentration semiconductor substrate HS from the source electrode S on the first surface Sf1 and then reaches the drain electrode D from the low-concentration semiconductor layer LS again. Therefore, in this case, a resistance component from the source electrode S toward the drain electrode D in the MOSFET is set to be a resistance obtained by combining resistances Ra and Rc in a vertical direction of the substrate and a resistance Rb in a horizontal direction of the substrate. Therefore, when compared with FIG. 13A, the resistance Rb in the horizontal direction of the substrate also significantly affects the resistance of the entire device.
Consequently, in order to reduce the resistance Rb, the metal plate 116 (see FIG. 12) having a low resistance is provided on the second surface Sf2 (rear surface) of the substrate. The metal plate is made of, for example, Cu, Fe, Al, Ag or the like.
Cu, Fe, Al or Ag is adopted since those metals are inexpensive and realize a low resistance value of the metal plate 116 itself. However, all of those metals have low oxidation resistance and corrosion resistance. Thus, for example, long-term storage thereof may oxidize and discolor the metal plate. The discoloration of the metal plate adversely affects the resistance value of the metal plate and deteriorates adhesion to a dicing sheet in an assembly operation. Thus, the discoloration is a significant factor that causes trouble such as chip scattering in a dicing operation.